Conventionally, there are known active-matrix display devices in which a plurality of gate bus lines (scanning signal lines) and a plurality of source bus lines (video signal lines) are arranged in a grid pattern, and a plurality of pixel formation portions are arranged in a matrix so as to correspond to their respective intersections of the gate bus lines and the source bus lines. Each of the pixel formation portions includes a TFT (thin-film transistor), which is a switching element having a gate terminal connected to a gate bus line passing through its corresponding intersection and a source terminal connected to a source bus line passing through the intersection, and also includes a pixel capacitance for holding a pixel value. Such an active-matrix display device is also provided with a gate driver (scanning signal line driver circuit) for driving the gate bus lines and a source driver (video signal line driver circuit) for driving the source bus lines.
Video signals, each indicating a pixel value, are transmitted by the source bus lines, but it is not possible for the source bus lines to concurrently (simultaneously) transmit video signals that indicate pixel values for a plurality of rows. Accordingly, video signals are sequentially written to the pixel capacitances in the pixel formation portions arranged in a matrix, on a row-by-row basis. Therefore, the gate driver includes a multiple-stage shift register such that the gate bus lines are each sequentially selected for a predetermined period. This shift register circuit is integrally formed on a substrate (where the TFTs are formed), and such a configuration is called a monolithic gate driver.
In this monolithic-gate-driver display panel, clock signals required for operating the shift register are provided to stages of the shift register through wiring lines arranged outside the periphery of the panel for the purpose of supplying signals to the driver circuit. The clock signals should normally be provided to TFTs included in the shift register, and therefore, an area for laying out the shift register is required to stretch out from where the wiring lines for supplying the driver circuit with signals are arranged to where the pixel formation portions are arranged. This is one of the factors that increase the extent of a shift register layout area, and in particular, any display device with a shift register operating on the basis of a number of clock signals tends to have a large shift register layout area.
Furthermore, in general active-matrix liquid crystal display devices, auxiliary capacitance lines are provided in parallel with gate bus lines, forming auxiliary capacitances through capacitive coupling with pixel electrodes. In addition, an auxiliary capacitance trunk line is provided in a frame area for the purpose of providing a common potential to the auxiliary capacitance lines. The auxiliary capacitance trunk line has the auxiliary capacitance lines commonly connected thereto, and therefore, in general, it is often the case that the auxiliary capacitance trunk line is provided in the frame area between the gate driver and the display area.
In this regard, Japanese Laid-Open Patent Publication No. 2007-10900 discloses a configuration in which auxiliary capacitance lines are connected to a source signal line of a scanning signal line driver circuit via a shared line equivalent to the auxiliary capacitance trunk line. Moreover, Japanese Laid-Open Patent Publication No. 10-48663 discloses a configuration in which first and second auxiliary capacitance lines are connected to a source voltage line and a ground voltage line, respectively, of a scanning signal line driver circuit. With this configuration, auxiliary capacitance resistance is reduced, and the operation of the driver circuit is stabilized.